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The Journal of The Korea Institute of Intelligent Transport Systems Vol.10 No.2 pp.77-83
18000-3 PJM 모드 태그의 동기부 및 복조부 하드웨어 설계
Hardware Design of the Synchronizer and the Demodulator of a 18000-3 PJM Mode Tag
Abstract
In this paper, we present the design procedure of the synchronizer and the demodulator of a 13.56MHz RFID PJM tag, which was standardized in ISO 18000-3 mode 3. We optimize the algorithms in order to minimize the number of registers and implement them based on international standard. The designed module is simulated by Modelsim and FPGA. The synchronizer is composed of 3 correlators that is implemented by 1,024(16bit×64cycle) registers. The demodulator is composed of 2 correlators that is implemented by 128(2bit×64cycle) registers. The simulation performed with the demodulator integrated with the synchronizer shows that it works at about 87% success rate with the test data of SNR -2dB and 100% with those of SNR 4dB.
